Assassyn: A Unified Abstraction for Architectural Simulation and Implementation
摘要
The continuous growth of on-chip transistors driven by technology scaling urges architecture developers to design and implement novel architectures to effectively utilize the excessive on-chip resources.Due to the challenges of programming in register-transfer level (RTL) languages, performance modeling based on cycle-accurate simulation is typically developed alongside hardware implementation, allowing the exploration of high-level design decisions before dealing with the error-prone, low-level RTL details. However, this approach also introduces new challenges in coordinating and aligning separate codebases.In this paper, we address this issue by presenting Assassyn, a unified, high-level, and general-purpose programming framework for architectural simulation and implementation. By taking advantage of asynchronous event handling, a widely existing behavior in both hardware design and implementation and software engineering, a general-purpose, and high-level programming abstraction is proposed to mitigate the difficulties of RTL programming. Moreover, the unified programming interface naturally enables an accurate and faithful alignment between performance modeling and RTL implementation.Our evaluation demonstrates that Assassyn high-level programming interface is sufficiently expressive to support the implementation of a wide range of architectures, including architectural components, application-specific accelerators, and even a CPU. All the generated cycle-accurate simulation models perfectly align with the generated RTL simulations, while achieving 1.4-6× simulation speedup. The generated RTL achieves comparable perf/area compared to handcrafted RTL, and 6× perf/area compared to high-level synthesis generated RTL code.
